View AM29BDS320G_5860141.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

october 1, 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. AM29BDS320G data sheet publication number 27243 revision b amendment 1 issue date october 1, 2003
this page left intentionally blank.
publication number 27243 revision b amendment 1 issue date october 1, 2003 preliminary AM29BDS320G 32 megabit (2 m x 16-bit), 1.8 volt-only simultaneous read/write, burst mode flash memory data sheet distinctive characteristics architectural advantages ? single 1.8 volt read, program and erase (1.65 to 1.95 volt) ? manufactured on 0.17 m process technology ? enhanced versatileio? (v io ) feature ? device generates data output voltages and tolerates data input voltages as determined by the voltage on the v io pin ? 1.8v and 3v compatible i/o signals ? simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in other bank ? zero latency between read and write operations ? four bank architecture: 8mb/8mb/8mb/8mb ? programmable burst interface ? 2 modes of burst read operation ? linear burst: 8, 16, and 32 words with wrap-around ? continuous sequential burst ? sector architecture ? eight 8 kword sectors and sixty-two 32 kword sectors ? banks a and d each contain four 8 kword sectors and fifteen 32 kword sectors; banks b and c each contain sixteen 32 kword sectors ? eight 8 kword boot sectors, four at the top of the address range, and four at the bottom of the address range ? minimum 1 million erase cycle guarantee per sector ? 20-year data retention at 125c ? reliable operation for the life of the system ? 64-ball fbga package performance charcteristics ? read access times at 54/40 mhz (at 30 pf) ? burst access times of 13.5/20 ns ? asynchronous random access times of 70 ns ? initial synchronous access times as fast as 87.5/95 ns ? power dissipation (typical values, c l = 30 pf) ? burst mode read: 10 ma ? simultaneous operation: 25 ma ? program/erase: 15 ma ?standby mode: 0.2 a hardware features ? sector protection ? software command sector locking ? reduced wait-state handshaking feature available ? provides host system with minimum possible latency by monitoring rdy ? hardware reset input (reset#) ? hardware method to reset the device for reading array data ? wp# input ? write protect (wp#) function protects sectors 0 and 1 (bottom boot), or sectors 68 and 69 (top boot), regardless of sector protect status ? acc input: acceleration function reduces programming time; all sectors locked when acc = v il ? cmos compatible inputs, cmos compatible outputs ? low v cc write inhibit software features ? supports common flash memory interface (cfi) ? software command set compatible with jedec 42.4 standards ? backwards compatible with am29f and am29lv families ? data# polling and toggle bits ? provides a software method of detecting program and erase operation completion ? erase suspend/resume ? suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences
2AM29BDS320G 27243b1 october 1, 2003 preliminary general description the AM29BDS320G is a 32 mbit, 1.8 volt-only, simultaneous read/write, burst mode flash memory device, organized as 2,097,152 words of 16 bits each. this device uses a single v cc of 1.65 to 1.95 v to read, program, and erase the mem- ory array. the device supports enhanced v io to offer up to 3v compatible inputs and outputs. a 12.0-volt v id may be used for faster program performance if de- sired. the device can also be programmed in standard eprom programmers. at 54 mhz, the device provides a burst access of 13.5 ns at 30 pf with a latency of 87.5 ns at 30 pf. at 40 mhz, the device provides a burst access of 20 ns at 30 pf with a latency of 95 ns at 30 pf. the device operates within the industrial tem- perature range of -40c to +85c. the device is offered in the 64-ball fbga package. the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into four banks. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank, with zero latency. this releases the system from waiting for the completion of program or erase operations. the device is divided as shown in the following table: the enhanced versatileio? (v io ) control allows the host system to set the volt- age levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. this allows the device to operate in 1.8 v an d 3 v system environments as required. the device uses chip enable (ce#), write enable (we#), address valid (avd#) and output enable (oe#) to control asynchronous read and write operations. for burst operations, the device additionally requires ready (rdy), and clock (clk). this implementation allows easy interface with minimal glue logic to a wide range of microprocessors/microcontrollers for high performance read operations. the burst read mode feature gives system designers flexibility in the interface to the device. the user can preset the bu rst length and wrap through the same memory space, or read the fl ash array in continuous mode. the clock polarity feature provides system designers a choice of active clock edges, either rising or falling. the active clock edge initiates burst accesses and determines when data will be output. the device is entirely command set compatible with the jedec 42.4 single- power-supply flash standard . commands are written to the command regis- ter using standard microprocessor write timing. register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. bank quantity size a 48 kwords 15 32 kwords b 16 32 kwords c 16 32 kwords d 15 32 kwords 48 kwords
october 1, 2003 27243b1 AM29BDS320G 3 preliminary write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read b oot-up firmware from the flash memory device. the host system can detect whether a program or erase operation is complete by using the device status bit dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to reading array data. the sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automat- ically inhibits write operations during power transitions. the device also offers two types of data protection at the sector level. the sector lock/unlock com- mand sequence disables or re-enables both program and erase operations in any sector. when at v il , wp# locks sectors 0 and 1 (bottom boot device) or sec- tors 68 and 69 (top boot device). the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consump- tion is greatly reduced in both modes. spansion flash technology combines year s of flash memory manufacturing expe- rience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via fowler- nordheim tunnelling. the data is programmed using hot electron injection.
4AM29BDS320G 27243b1 october 1, 2003 preliminary table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . .6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 block diagram of simultaneous operation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .8 connection diagram . . . . . . . . . . . . . . . . . . . . . . . .9 special handling instructions for fbga package .......................... 9 input/output descriptions . . . . . . . . . . . . . . . . . . . 10 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ordering information . . . . . . . . . . . . . . . . . . . . . . . 11 device bus operations . . . . . . . . . . . . . . . . . . . . . . 12 table 1. device bus operations ..........................................12 enhanced versatileio? (v io ) control ............................................ 12 requirements for asynchronous read operation (non-burst) ........................................................................ 12 requirements for synchronous (burst) read operation ......... 13 8-, 16-, and 32-word linear burst with wrap around ............. 14 table 2. burst address groups ............................................14 burst mode configuration register ................................................. 14 reduced wait-state handshaking option ..................................... 14 simultaneous read/write operations with zero latency ....... 15 writing commands/command sequences ................................... 15 accelerated program operation ...................................................... 15 autoselect functions ............................................................................ 16 standby mode ......................................................................................... 16 automatic sleep mode ......................................................................... 16 reset#: hardware reset input ........................................................ 16 output disable mode ........................................................................... 17 hardware data protection ................................................................. 17 write protect (wp#) ........................................................................... 17 low v cc write inhibit ........................................................................ 17 write pulse ?glitch? protection ....................................................... 18 logical inhibit .......................................................................................... 18 power-up write inhibit ...................................................................... 18 v cc and v io power-up and power-down sequencing ............. 18 common flash memory interface (cfi) . . . . . . . 18 table 3. cfi query identification string ...............................19 system interface string..................................................... 19 table 5. device geometry definition......................................... 20 table 6. primary vendor-specific extended query................. 21 table 7. sector address table...................................................... 22 command definitions . . . . . . . . . . . . . . . . . . . . . . 25 reading array data ............................................................................. 25 set burst mode configuration register command sequence 25 figure 1. synchronous/asynchronous state diagram ............. 26 read mode setting ............................................................................... 26 programmable wait state configuration ...................................... 26 table 8. programmable wait state settings ..........................27 reduced wait-state handshaking option .................................... 27 table 9. initial access cycles vs. frequency ..........................27 standard handshaking operation ................................................... 28 table 10. wait states for standard handshaking ...................28 burst read mode configuration ...................................................... 28 table 11. burst read mode settings ....................................28 burst active clock edge configuration ......................................... 28 rdy configuration .............................................................................. 29 configuration register ........................................................................ 29 table 12. burst mode configuration register ........................ 29 sector lock/unlock command sequence .................................... 29 reset command ................................................................................... 30 autoselect command sequence ..................................................... 30 table 13. device ids ......................................................... 31 program command sequence ............................................................31 unlock bypass command sequence ................................................31 figure 2. erase operation.................................................. 32 chip erase command sequence ......................................................32 sector erase command sequence ................................................... 33 erase suspend/erase resume commands .....................................34 figure 3. program operation.............................................. 35 command definitions .......................................................................... 36 table 14. command definitions ......................................... 36 write operation status . . . . . . . . . . . . . . . . . . . . 37 dq7: data# polling ..............................................................................37 figure 4. data# polling algorithm....................................... 38 rdy: ready .............................................................................................38 dq6: toggle bit i ..................................................................................39 figure 5. toggle bit algorithm............................................ 40 dq2: toggle bit ii ................................................................................ 40 table 15. dq6 and dq2 indications .................................... 41 reading toggle bits dq6/dq2 ........................................................ 41 dq5: exceeded timing limits ........................................................... 41 dq3: sector erase timer .................................................................. 42 table 16. write operation status ........................................ 42 absolute maximum ratings . . . . . . . . . . . . . . . . . 43 figure 6. maximum negative overshoot waveform ............... 43 figure 7. maximum positive overshoot waveform................. 43 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 43 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 44 cmos compatible .............................................................................. 44 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 8. test setup ......................................................... 45 table 17. test specifications .............................................. 45 key to switching waveforms . . . . . . . . . . . . . . . . 45 figure 9. input waveforms and measurement levels............. 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 10. v cc and v io power-up diagram ........................... 46 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47 synchronous/burst read .....................................................................47 figure 11. clk synchronous burst mode read (rising active clk)............................................................ 48 figure 12. clk synchronous burst mode read (falling active clock) ........................................................ 49 figure 13. synchronous burst mode read ............................ 50 figure 14. 8-word linear burst with wrap around................. 50 figure 15. burst with rdy set one cycle before data............ 51 figure 16. reduced wait-state handshaking burst mode read starting at an even address .............................................. 52 figure 17. reduced wait-state handshaking burst mode read starting at an odd address................................................ 53 asynchronous read ..............................................................................54 figure 18. asynchronous mode read with latched addresses . 54 figure 19. asynchronous mode read................................... 55 figure 20. reset timings ................................................... 56
october 1, 2003 27243b1 AM29BDS320G 5 preliminary erase/program operations ................................................................ 57 figure 21. asynchronous program operation timings............. 58 figure 22. alternate asynchronous program operation timings 59 figure 23. synchronous program operation timings .............. 60 figure 24. alternate synchronous program operation timings 61 figure 25. chip/sector erase command sequence................. 62 figure 26. accelerated unlock bypass programming timing .... 63 figure 27. data# polling timings (during embedded algorithm) 64 figure 28. toggle bit timings (during embedded algorithm)... 64 figure 29. synchronous data polling timings/toggle bit timings . 65 figure 30. latency with boundary crossing .......................... 66 figure 31. latency with boundary crossing into program/erase bank ................................................... 67 figure 32. example of wait states insertion (standard handshaking device) ........................................................ 68 figure 33. back-to-back read/write cycle timings ............... 69 erase and programming performance . . . . . . . . 70 fbga ball capacitance . . . . . . . . . . . . . . . . . . . . . 70 data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 physical dimensions . . . . . . . . . . . . . . . . . . . . . . . 71 vbd064?64-ball fine-pitch ball grid array (fbga) 8 x 9 mm package ..................................................................................71 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . 72
6AM29BDS320G 27243b1 october 1, 2003 preliminary product selector guide notes: 1. speed options ending in ?3? and ?8? indicate the ?reduced wait-state handshaking? option, which speeds initial synchronous accesses for even addresses. 2. speed options ending in ?4? and ?9? indi cate the ?standard handshaking? option. 3. see the ac characteristics section of th is data sheet for full specifications. part number AM29BDS320G burst frequency 54 mhz 40 mhz speed option v cc = 1.65 ? 1.95 v, v io = 2.7 ? 3.15 v d3, d4 c3, c4 v cc, v io = 1.65 ? 1.95 v d8, d9 c8, c9 max initial synchronous access time, ns (t iacc ) reduced wait-state handshaking: even address 87.5 95 max initial synchronous access time, ns (t iacc ) reduced wait-state handshaking: odd address; or standard handshaking 106 120 max burst access time, ns (t bacc ) 13.5 20 max asynchronous access time, ns (t acc ) 70 90 max ce# access, ns (t ce ) max oe# access, ns (t oe ) 13.5 20
october 1, 2003 27243b1 AM29BDS320G 7 preliminary block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# reset# wp# acc ce# oe# dq15 ? dq0 data latch y-gating cell matrix address latch a20?a0 rdy buffer rdy burst state control burst address counter avd# clk
8AM29BDS320G 27243b1 october 1, 2003 preliminary block diagram of simultaneous operation circuit v ss v cc v io bank b address reset# acc we# ce# avd# rdy dq15?dq0 wp# state control & command register bank b x-decoder y-decoder latches and control logic bank a x-decoder y-decoder latches and control logic dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 bank c y-decoder x-decoder latches and control logic bank d y-decoder x-decoder latches and control logic oe# status control a20?a0 a20?a0 a20?a0 a20?a0 a20?a0 bank c address bank d address bank a address
october 1, 2003 27243b1 AM29BDS320G 9 preliminary connection diagram special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultra- sonic cleaning methods. the package and/ or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged peri- ods of time. a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 a7 b7 c7 d7 e7 f7 g7 h7 dq15 v ss nc a16 a15 a14 a12 a13 a8 b8 c8 d8 e8 f8 g8 h8 nc nc nc v ss v io nc nc nc dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 a20 a18 acc rdy dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 b1 c1 d1 e1 f1 g1 h1 v ss nc v io avd# wp# clk v cc nc 64-ball fine-pitch ball grid array (top view, balls facing down)
10 AM29BDS320G 27243b1 october 1, 2003 preliminary input/output descriptions a20-a0 = address inputs dq15-dq0 = data input/output ce# = chip enable input. asynchronous relative to clk for the burst mode. oe# = output enable input. asynchronous relative to clk for the burst mode. we# = write enable input. v cc = device power supply (1.65 ? 1.95 v). v io = input & output buffer power supply (either 1.65 ? 1.95 v or 2.7 ? 3.15 v). v ss = ground nc = no connect; not connected internally rdy = ready output; indicates the status of the burst read. low = data not valid at expected time. high = data valid. clk = clk is not required in asynchronous mode. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. avd# = address valid input. indicates to device that the valid address is present on the address inputs (a20?a0). low = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched. high = device ignores address inputs reset# = hardware reset input. low = device resets and returns to reading array data wp# = hardware write protect input. at v il , disables program and erase functions in the two outermost sectors. should be at v ih for all other conditions. acc = at v id , accelerates programming; automatically places device in unlock bypass mode. at v il , locks all sectors. should be at v ih for all other conditions. logic symbol 21 16 dq15?dq0 a20?a0 ce# oe# we# reset# clk rdy avd# wp# acc
october 1, 2003 27243b1 AM29BDS320G 11 preliminary ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local sales office or representative to confirm availability of specific valid combinations and to check on newly released combinations. note: for the AM29BDS320G, the last digit of the speed grade specifies the v io range of the device. speed options ending in ?8? and ?9? (e.g., d8, d9) indicate a 1.8 volt v io range. speed grades ending in ?3? and ?4? (e.g., d3, d4) indicate a 3.0 volt v io range. AM29BDS320G t d 8 vm i temperature range i = industrial (?40 c to +85 c) package type vm = 64-ball fine-pitch grid array (fbga) 0.80 mm pitch, 8 x 9 mm package (vbd064) v io and handshaking features 8 = 1.8 v vio, reduced wait-state handshaking 9 = 1.8 v vio, standard handshaking 3 = 3 v vio, reduced wait-state handshaking 4 = 3 v vio, standard handshaking clock rate/asynchronous speed d = 54 mhz/70 ns c = 40 mhz/90 ns boot code sector architecture t = top boot sector b = bottom boot sector device number/description AM29BDS320G 32 megabit (2 m x 16-bit) cmos flash memory, simultaneous read/write, burst mode flash memory, 1.8 volt-only read, program, and erase valid combinations burst frequency (mhz) v io range order number package marking AM29BDS320Gtd8 AM29BDS320Gbd8 vmi bs320gtd8v bs320gbd8v 54 1.65?1.95v AM29BDS320Gtd9 AM29BDS320Gbd9 bs320gtd9v bs320gbd9v AM29BDS320Gtc8 AM29BDS320Gbc8 bs320gtc8v bs320gbc8v 40 AM29BDS320Gtc9 AM29BDS320Gbc9 bs320gtc9v bs320gbc9v AM29BDS320Gtd3 AM29BDS320Gbd3 vmi bs320gtd3v bs320gbd3v 54 2.7?3.15v AM29BDS320Gtd4 AM29BDS320Gbd4 bs320gtd4v bs320gbd4v AM29BDS320Gtc3 AM29BDS320Gbc3 bs320gtc3v bs320gbc3v 40 AM29BDS320Gtc4 AM29BDS320Gbc4 bs320gtc4v bs320gbc4v
12 AM29BDS320G 27243b1 october 1, 2003 preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is com- posed of latches that store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machin e. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and con- trol levels they require, and the resu lting output. the following subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic 0, h = logic 1, x = don?t care, s = stable logic 0 or 1 but no transitions. note: default active edge of clk is the rising edge. enhanced versatileio? (v io ) control the enhanced versatileio (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data and address inputs to the same voltage level that is asserted on the v io pin. the device is available with either 1.65?1.95 or 2.7?3.15 v io . this allows the device to operate in 1.8 v or 3 v system environments as required. for example, a v io of 2.7 ? 3.15 volts allows for i/o at the 3 volt level, driving and receiving signals to and from other 3 v devices on the same bus. requirements for asynchronous read operation (non-burst) to read data from the memory array, the system must first assert a valid address on a20?a0, while driving avd# and ce# to v il . we# should remain at v ih . the rising edge of avd# latches the address. the data will appear on dq15?dq0. operation ce# oe# we# a20?0 dq15?0 reset# clk (see note) avd# asynchronous read - addresses latched l l h addr in i/o h x asynchronous read - addresses steady state l l h addr in i/o h x l asynchronous write l h l addr in i/o h l l synchronous write l h l addr in i/o h standby (ce#) h x x high z high z h x x hardware reset x x x high z high z l x x burst read operations load starting burst address l x h addr in x h advance burst to next address with appropriate data presen ted on the data bus llhhigh z burst data out hh terminate current burst read cycle h x h high z high z h x terminate current burst read cycle via reset# x x h high z high z l x x terminate current burst read cycle and start new burst read cycle lxhhigh zi/o h
october 1, 2003 27243b1 AM29BDS320G 13 preliminary since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. requirements for synchronous (burst) read operation the device is capable of continuous sequential burst operation and linear burst operation of a preset length. when the device first powers up, it is enabled for asynchronous read operation. prior to entering burst mode, the system should determine how many wait states are desired for the initial word (t iacc ) of each burst access, what mode of burst operation is desired, which edge of the clock will be the active clock edge, and how the rdy signal will transition with valid data. the system would then write the burst mode configuration register command sequence. see ?set burst mode configuration register command sequence? and ?command definitions? for fur- ther details. once the system has written the ?set burst mode configuration register? com- mand sequence, the device is enabled for synchronous reads only. the initial word is output t iacc after the active edge of the first clk cycle. sub- sequent words are output t bacc after the active edge of each successive clock cycle, which automatically increments the internal address counter. note that the device has a fixed internal address boundary that occurs every 64 words, starting at address 00003fh. during the time the device is outputting data at this fixed internal address boundary (address 00003fh, 00007fh, 0000bfh, etc.), a two cycle latency occurs before data appears for the next address (address 000040h, 000080h, 0000c0h, etc.). the rdy output indicates this condition to the system by pulsing low. for standard handshaking devices, there is no two cycle latency between 3fh and 40h (or addresses offset from 3f and 40h by a multiple of 64). see ta b l e 1 0 . for reduced wait-state handshaking devices, if the address latched is 3dh (or off- set from 3dh by a multiple of 64), an additional cycle latency occurs prior to the initial access. if the address latched is 3eh (or offset from 3eh by a multiple of 64) two additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3fh and 40h (or offset from 3fh by a multiple of 64) will not oc- cur. for 3fh latched addresses (or offset from 3fh by a multiple of 64) three additional cycle latency occurs prior to the initial access and the 2 cycle latency between 3fh and 40h (or offset from these addresses by a multiple of 64) will not occur. the device will continue to output sequen tial burst data, wrapping around to ad- dress 000000h after it reaches the highest addressable memory location, until the system drives ce# high, reset# low, or avd# low in conjunction with a new address. see table 1, ?device bus operations,? on page 12 . if the host system crosses the bank boundary while reading in burst mode, and the device is not programming or erasing, a two-cycle latency will occur as de- scribed above in the subsequent bank. if the host system crosses the bank
14 AM29BDS320G 27243b1 october 1, 2003 preliminary boundary while the device is programming or erasing, the device will provide read status information. the clock will be ignored. after the host has completed status reads, or the device has completed the program or erase operation, the host can restart a burst operation using a new address and avd# pulse. if the clock frequency is less than 6 mh z during a burst mode operation, addi- tional latencies will occur. rdy indicates the length of the latency by pulsing low. 8-, 16-, and 32-word linear burst with wrap around the remaining three modes are of the linear wrap around design, in which a fixed number of words are read from consecutive addresses. in each of these modes, the burst addresses read are determined by the group within which the starting address falls. the groups are sized acco rding to the number of words read in a single burst sequence for a given mode (see ta b l e 2 .) ta b l e 2 . burst address groups as an example: if the starting address in the 8-word mode is 39h, the address range to be read would be 38-3fh, and the burst sequence would be 39-3a-3b- 3c-3d-3e-3f-38h-etc. the burst sequence begins with the starting address writ- ten to the device, but wraps back to the first address in the selected group. in a similar fashion, the 16-word and 32-word linear wrap modes begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. note that in these three burst read modes the address pointer does not cross the boundary that occurs every 64 words; thus, no wait states are inserted (except during the ini- tial access). the rdy pin indicates when data is valid on the bus. the devices can wrap through a maximum of 128 words of data (8 words up to 16 times, 16 words up to 8 times, or 32 words up to 4 times) before requiring a new synchronous access (latching of a new address). burst mode configuration register the device uses a configuration register to set the various burst parameters: number of wait states, burst read mode, active clock edge, rdy configuration, and synchronous mode active. reduced wait-state handshaking option the device can be equipped with a reduced wait-state handshaking feature that allows the host system to simply monitor the rdy signal from the device to de- termine when the initial word of burst data is ready to be read. the host system should use the programmable wait state configuration to set the number of wait states for optimal burst mode operation. the initial word of burst data is indicated by the rising edge of rdy after oe# goes low. the presence of the reduced wait-state handshaking feature may be verified by writing the autoselect command sequence to the device. see ?autoselect com- mand sequence? for details. mode group size group address ranges 8-word 8 words 0-7h, 8-fh, 10-17h, ... 16-word 16 words 0-fh, 10-1fh, 20-2fh, ... 32-word 32 words 00-1fh, 20-3fh, 40-5fh, ...
october 1, 2003 27243b1 AM29BDS320G 15 preliminary for optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system mu st set the appropriate number of wait states in the flash device depending on clock frequency and the presence of a boundary crossing. see ?set burst mode configuration register command se- quence? section on page 25 section for more information. the device will automatically delay rdy and data by one ad ditional clock cycle when the starting address is odd. the autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. see the ?autoselect com- mand sequence? section for more information. simultaneous read/write oper ations with zero latency this device is capable of reading data from one bank of memory while program- ming or erasing in another bank of memory. an erase operation may also be suspended to read from or program to another location within the same bank (ex- cept the sector being erased). figure 33, ?back-to-back read/write cycle timings,? on page 69 shows how read and write cycles may be initiated for simul- taneous operation with zero latency. refer to the dc characteristics table for read-while-program and read-while-erase current specifications. writing commands/command sequences the device has the capability of performing an asynchronous or synchronous write operation. during a synchronous write operation, to write a command or command sequence (which includes progra mming data to the device and erasing sectors of memory), the system must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih . when writing commands or data. du ring an asynchronous write op- eration, the system must dr ive ce#, we#, and clk to v il and oe# to v ih when providing an address, command, and da ta. the asynchronous and synchronous programing operation is independent of the set device read mode bit in the burst mode configuration register. the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypa ss mode, only two write cycles are re- quired to program a word, instead of four. an erase operation can erase one sector, multiple sectors, or the entire device. table 8, ?programmable wait state settings,? on page 27 indicates the address space that each sector occupies. the de vice address space is divided into four banks: banks b and c contain only 32 kword sectors, while banks a and d contain both 8 kword boot sectors in addition to 32 kword sectors. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? is the address bits required to uniquely select a sector. i cc2 in the dc characteristics table represents the active current specification for the write mode. the ac characteristics section contains timing specification ta- bles and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. acc is primarily intended to allow faster ma nufacturing throughput at the factory. if the system asserts v id on this input, the device automatically enters the afore- mentioned unlock bypass mode and uses the higher voltage on the input to reduce the time required for program operations. the system would use a two-
16 AM29BDS320G 27243b1 october 1, 2003 preliminary cycle program command sequence as required by the unlock bypass mode. re- moving v id from the acc input returns the device to normal operation. note that sectors must be unlocked prior to raising acc to v id . note that the acc pin must not be at v id for operations other than accelerated programming, or device dam- age may result. in addition, the acc pin must not be left floating or unconnected; inconsistent behavior of the device may result . when at v il , acc locks all sectors. acc should be at v ih for all other conditions. autoselect functions if the system writes the autoselect comma nd sequence, the device enters the au- toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq15?dq0. autoselect mode may only be entered and used when in the asynchronous read mode. refer to the ?autoselect command sequence? section on page 30 section for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access, before it is ready to read data. if the device is deselected during erasure or programming, the device draws ac- tive current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. while in asynchronous mode, the device automatica lly enables this mode when addresses remain stable for t acc + 60 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. while in synchronous mode, the de- vice automatically enables this mode when either the first active clk edge occurs after t acc or the clk runs slower than 5mhz. note that a new burst operation is required to provide new data. i cc4 in the ?dc characteristics? section on page 44 represents the automatic sleep mode current specification. reset#: hardware reset input the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low for at least a period of t rp , the device im- mediately terminates any operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the de- vice is ready to accept another command sequence, to ensure data integrity.
october 1, 2003 27243b1 AM29BDS320G 17 preliminary current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.2 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.2 v, the standby current will be greater. reset# may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or erase operation, the device requires a time of t ready (during embedded algorithms) before the device is ready to read data again. if reset# is asserted when a program or erase operation is not ex- ecuting, the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after reset# returns to v ih . refer to the ac characteristics tables for reset# parameters and to figure 20, ?reset timings,? on page 56 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 14, ?command definitions,? on page 36 for command definitions). the device offers two types of data protection at the sector level: ? the sector lock/unlock command sequence disables or re-enables both pro- gram and erase operat ions in any sector. ? when wp# is at v il , sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top boot) are locked. ? when acc is at v il , all sectors are locked. the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. write protect (wp#) the write protect (wp#) input provides a hardware method of protecting data without using v id . if the system asserts v il on the wp# pin, the device disables program and erase functions in sectors 0 and 1 (bottom boot) or sectors 68 and 69 (top boot). if the system asserts v ih on the wp# pin, the device reverts to whether the two outermost 8k byte boot sectors were last set to be protected or unprotected. note that the wp# pin must not be left floating or unconnected; inconsistent be- havior of the device may result. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro- tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the sys-
18 AM29BDS320G 27243b1 october 1, 2003 preliminary tem must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. v cc and v io power-up and power-down sequencing the device imposes no restrictions on v cc and v io power-up or power-down se- quencing. asserting reset# to v il is required during the entire v cc and v io power sequence until the respective supplies reach their operating voltages. once v cc and v io attain their respective operating voltages, de-assertion of reset# to v ih is permitted. common flash memory interface (cfi) the common flash interface (cfi) specificati on outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id-independent, and forward- and back- ward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 3-6. to ter- minate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au- toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 3-6. the system must write the reset command to return the device to the reading array data. for further information, please refer to the cfi specification and cfi publication 100, available via the web at the following url: http://www.amd.com/flash/cfi . alternatively, contact a sales office or representative for copies of these documents.
october 1, 2003 27243b1 AM29BDS320G 19 preliminary ta b l e 3 . cfi query identification string table 4. system interface string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses data description 1bh 0017h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0019h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0004h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
20 AM29BDS320G 27243b1 october 1, 2003 preliminary ta b l e 5 . device geometry definition addresses data description 27h 0016h device size = 2 n byte 28h 29h 0001h 0000h flash device interface descriptio n (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of bytes in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0003h 0000h 0040h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 003dh 0000h 0000h 0001h erase block region 2 information 35h 36h 37h 38h 0003h 0000h 0040h 0000h erase block region 3 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information
october 1, 2003 27243b1 AM29BDS320G 21 preliminary ta b l e 6 . primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0004h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0001 = 0.17 m 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0005h sector protect/unprotect scheme 04 = 29lv800 mode 4ah 0033h simultaneous operation number of sectors in all banks except boot block 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 00xxh top/bottom boot sector flag 02h = bottom boot device , 03h = top boot device 50h 0000h program suspend. 00h = not supported 57h 0004h bank organization: x = number of banks 58h 0013h bank a region information. x = number of sectors in bank 59h 0010h bank b region information. x = number of sectors in bank 5ah 0010h bank c region information. x = number of sectors in bank 5bh 0013h bank d region information. x = number of sectors in bank
22 AM29BDS320G 27243b1 october 1, 2003 preliminary ta b l e 7 . sector address table sector sector size (x16) address range bank d sa0 8 kwords 000000h-001fffh sa1 8 kwords 002000h-003fffh sa2 8 kwords 004000h-005fffh sa3 8 kwords 006000h-007fffh sa4 32 kwords 008000h-00ffffh sa5 32 kwords 010000h-017fffh sa6 32 kwords 018000h-01ffffh sa7 32 kwords 020000h-027fffh sa8 32 kwords 028000h-02ffffh sa9 32 kwords 030000h-037fffh sa10 32 kwords 038000h-03ffffh sa11 32 kwords 040000h-047fffh sa12 32 kwords 048000h-04ffffh sa13 32 kwords 050000h-057fffh sa14 32 kwords 058000h-05ffffh sa15 32 kwords 060000h-067fffh sa16 32 kwords 068000h-06ffffh sa17 32 kwords 070000h-077fffh sa18 32 kwords 078000h-07ffffh
october 1, 2003 27243b1 AM29BDS320G 23 preliminary bank c sa19 32 kwords 080000h-087fffh sa20 32 kwords 088000h-08ffffh sa21 32 kwords 090000h-097fffh sa22 32 kwords 098000h-09ffffh sa23 32 kwords 0a0000h-0a7fffh sa24 32 kwords 0a8000h-0affffh sa25 32 kwords 0b0000h-0b7fffh sa26 32 kwords 0b8000h-0bffffh sa27 32 kwords 0c0000h-0c7fffh sa28 32 kwords 0c8000h-0cffffh sa29 32 kwords 0d0000h-0d7fffh sa30 32 kwords 0d8000h-0dffffh sa31 32 kwords 0e0000h-0e7fffh sa32 32 kwords 0e8000h-0effffh sa33 32 kwords 0f0000h-0f7fffh sa34 32 kwords 0f8000h-0fffffh bank b sa35 32 kwords 100000h-107fffh sa36 32 kwords 108000h-10ffffh sa37 32 kwords 110000h-117fffh sa38 32 kwords 118000h-11ffffh sa39 32 kwords 120000h-127fffh sa40 32 kwords 128000h-12ffffh sa41 32 kwords 130000h-137fffh sa42 32 kwords 138000h-13ffffh sa43 32 kwords 140000h-147fffh sa44 32 kwords 148000h-14ffffh sa45 32 kwords 150000h-157fffh sa46 32 kwords 158000h-15ffffh sa47 32 kwords 160000h-167fffh sa48 32 kwords 168000h-16ffffh sa49 32 kwords 170000h-177fffh sa50 32 kwords 178000h-17ffffh sector sector size (x16) address range
24 AM29BDS320G 27243b1 october 1, 2003 preliminary bank a sa51 32 kwords 180000h-187fffh sa52 32 kwords 188000h-18ffffh sa53 32 kwords 190000h-197fffh sa54 32 kwords 198000h-19ffffh sa55 32 kwords 1a0000h-1a7fffh sa56 32 kwords 1a8000h-1affffh sa57 32 kwords 1b0000h-1b7fffh sa58 32 kwords 1b8000h-1bffffh sa59 32 kwords 1c0000h-1c7fffh sa60 32 kwords 1c8000h-1cffffh sa61 32 kwords 1d0000h-1d7fffh sa62 32 kwords 1d8000h-1dffffh sa63 32 kwords 1e0000h-1e7fffh sa64 32 kwords 1e8000h-1effffh sa65 32 kwords 1f0000h-1f7fffh sa66 8k words 1f8000h-1f9fffh sa67 8k words 1fa000h-1fbfffh sa68 8k words 1fc000h-1fdfffh sa69 8k words 1fe000h-1fffffh sector sector size (x16) address range
october 1, 2003 27243b1 AM29BDS320G 25 preliminary command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 14, ?command definitions,? on page 36 defines the valid register command sequences. note that writing incorrect ad- dress and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is required to return the device to normal operation. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data in asynchronous mode. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. after completing a pro- gramming operation in the erase suspend mode, the system may once again read array data with the same exception. see the ?erase suspend/erase resume commands? section on page 34 section for more information. the system must issue the reset command to return a bank to the read (or erase- suspend-read) mode if dq5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. see the ?reset command? section on page 30 section for more information. see also ?requirements for asynchronous read operation (non-burst)? and ?re- quirements for synchronous (burst) read operation? sections for more information. the asynchronous read and synchronous/burst read tables provide the read parameters, and figures 11 , 13 , and 18 show the timings. set burst mode configuration register command sequence the device uses a burst mode configuration register to set the various burst pa- rameters: number of wait states, burs t read mode, active clock edge, rdy configuration, and synchronous mode active. the burst mode configuration reg- ister must be set before the device will enter burst mode. the burst mode configuration register is loaded with a three-cycle command se- quence. the first two cycles are standard unlock sequences. on the third cycle, the data should be c0h, address bits a11?a0 should be 555h, and address bits a19?a12 set the code to be latched. the device will power up or after a hardware reset with the default setting, which is in asynchronous mode. the register must be set before the device can enter synchronous mode. the burst mode configu- ration register can not be changed during device operations (program, erase, or sector lock).
26 AM29BDS320G 27243b1 october 1, 2003 preliminary figure 1. synchronous/asynchronous state diagram read mode setting on power-up or hardware reset, the device is set to be in asynchronous read mode. this setting allows the system to en able or disable burst mode during sys- tem operations. address a19 determines th is setting: ?1? for asynchronous mode, ?0? for synchronous mode. programmable wait state configuration the programmable wait state feature informs the device of the number of clock cycles that must elapse after avd# is driven active before data will be available. this value is determined by the input frequency of the device. address bits a14? a12 determine the setting (see ta b l e 8 ). the wait state command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. the number of wait states that should be programmed into the device is directly related to the clock frequency. power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (a19 = 0) set burst mode configuration register command for asynchronous mode (a19 = 1)
october 1, 2003 27243b1 AM29BDS320G 27 preliminary ta b l e 8 . programmable wait state settings notes: 1. upon power-up or hardware reset, the default setting is seven wait states. 2. rdy will default to being active with data when the wait state setting is set to a total initial access cycle of 2. 3. assumes even address. it is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. a hardware reset will set the wait state to the default setting. reduced wait-state handshaking option if the device is equipped with the reduced wait-state handshaking option, the host system should set address bits a 14?a12 to 010 for a clock frequency of 40 mhz or to 011 for a clock frequency of 54 mhz for the system/device to execute at maximum speed. ta b l e 9 describes the typical number of clock cycles (wait states) for various conditions. ta b l e 9 . initial access cycles vs. frequency note: in the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (3fh, and addresses offset from 3fh by a multiple of 64). the autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. see the ?autoselect com- mand sequence? section for more information. a14 a13 a12 total initial access cycles 000 2 001 3 010 4 011 5 100 6 101 7 system frequency range even initial addr. odd initial addr. even initial addr. with boundary odd initial addr. with boundary device speed rating 6?11 mhz 2 2 3 4 40 mhz 12?23 mhz 2 3 4 5 24?33 mhz 3 4 5 6 34?40 mhz 4 5 6 7 40?47 mhz 4 5 6 7 54 mhz 48?54 mhz 5 6 7 8
28 AM29BDS320G 27243b1 october 1, 2003 preliminary standard handshaking operation for optimal burst mode performance on devices without the reduced wait-state handshaking option, the host system mu st set the appropriate number of wait states in the flash device depending on the clock frequency. ta b l e 1 0 describes the typical number of clock cycles (wait states) for various conditions with a14?a12 set to 101. table 10. wait states for standard handshaking * in the 8-, 16- and 32-word burst read mo des, the address pointer does not cross 64-word boundaries (3fh, and addresses offset from 3fh by a multiple of 64). burst read mode configuration the device supports four different burst read modes: continuous mode, and 8, 16, and 32 word linear wrap around mode s. a continuous sequence begins at the starting address and advances the address pointer until the burst operation is complete. if the highest address in the device is reached during the continuous burst read mode, the address pointer wr aps around to the lowest address. for example, an eight-word linear burst wi th wrap around begins on the starting burst address written to the device and then proceeds until the next 8 word boundary. the address pointer then returns to the first word of the burst se- quence, wrapping back to the starting location. the sixteen- and thirty-two linear wrap around modes operate in a fashion similar to the eight-word mode. ta b l e 1 1 shows the address bits and settings for the four burst read modes. table 11. burst read mode settings note: upon power-up or hardware reset the default setting is continuous. burst active clock edge configuration by default, the device will deliver data on the rising edge of the clock after the initial synchronous access time. subsequent outputs will also be on the following rising edges, barring any delays. the device can be set so that the falling clock conditions at address typical no. of clock cycles after avd# low 40/54 mhz initial address is even 7 initial address is odd 7 initial address is even, and is at boundary crossing* 7 initial address is odd, and is at boundary crossing* 7 burst modes address bits a16 a15 continuous 0 0 8-word linear wrap around 0 1 16-word linear wrap around 1 0 32-word linear wrap around 1 1
october 1, 2003 27243b1 AM29BDS320G 29 preliminary edge is active for all synchronous accesses. address bit a17 determines this set- ting; ?1? for rising active, ?0? for falling active. rdy configuration by default, the device is set so that the rdy pin will output v oh whenever there is valid data on the outputs. the device can be set so that rdy goes active one data cycle before active data. address bit a18 determines this setting; ?1? for rdy active with data, ?0? for rdy active one clock cycle before valid data. configuration register ta b l e 1 2 shows the address bits that determine the configuration register settings for various device functions. ta b l e 1 2 . burst mode configuration register note: device will be in the default state upon power-up or hardware reset. sector lock/unlock command sequence the sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. when the device is first powered up, all sectors are locked. to unlock a sector, the system must write the sector lock/ unlock command sequence. in the first and second cycles, the address must point to the bank that contains the sector(s) to be locked or unlocked. the first and second cycle data is 60h. in the third cycl e, the address must point to the target sector, and a6 is used to specify a lock (a6 = v il ) or unlock (a6 = v ih ) operation. the third cycle data is 60h. after the third cycle, the system can continue to lock or unlock additional sectors in the same bank or exit the sector lock/unlock se- quence by writing the reset command (f0h). it is not possible to read from the bank selected for sector lock/unlock operations. to enable such read operations, write the reset command. note that the last two outermost boot sectors can be locked by taking the wp# signal to v il . address bit function settings (binary) a19 set device read mode 0 = synchronous read (burst mode) enabled 1 = asynchronous mode (default) a18 rdy 0 = rdy active one clock cycle before data 1 = rdy active with data (default) a17 clock 0 = burst starts and data is output on the falling edge of clk 1 = burst starts and data is output on the rising edge of clk (default) a16 burst read mode 00 = continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around a15 a14 programmable wait state 000 = data is valid on the 2nd active clk edge after avd# transition to v ih 001 = data is valid on the 3rd active clk edge after avd# transition to v ih 010 = data is valid on the 4th active clk edge after avd# transition to v ih 011 = data is valid on the 5th active clk edge after avd# transition to v ih 100 = data is valid on the 6th active clk edge after avd# transition to v ih 101 = data is valid on the 7th active clk edge after avd# transition to v ih (default) a13 a12
30 AM29BDS320G 27243b1 october 1, 2003 preliminary reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys- tem was writing to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins (prior to the third cycle). this re- sets the bank to which the system was wr iting to the read mode. if the program command sequence is written to a bank th at is in the erase suspend mode, writ- ing the reset command returns that bank to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the op- eration is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autosele ct mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). the reset command is used to exit the sector lock/unlock sequence. this com- mand is required before reading from the bank selected for sector lock/unlock operations. autoselect command sequence the autoselect command sequence allows the host system to access the manu- facturer and device codes, and determine whether or not a sector is protected. table 14, ?command definitions,? on page 36 shows the address and data re- quirements. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autose- lect command may not be written while the device is actively programming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au- toselect command. the bank then enters the autoselect mode. no subsequent data will be made available if the autoselect data is read in synchronous mode. the system may read at any address within the same bank any number of times without initiating another autoselect co mmand sequence. the following table de- scribes the address requirements for the various autoselect functions, and the resulting data. ba represents the bank address, and sa represents the sector ad- dress. the device id is read in three cycles.
october 1, 2003 27243b1 AM29BDS320G 31 preliminary ta b l e 1 3 . device ids the system must write the reset command to return to the read mode (or erase- suspend-read mode if the bank wa s previously in erase suspend). program command sequence programming is a four-bus-cycle operat ion. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further con- trols or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. ta b l e 1 4 shows the address and data requirements for the program command sequence. when the embedded program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by monitoring dq7 or dq6/dq2. refer to the ?write operation status? section on page 37 section for information on these sta- tus bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware rese t immediately terminates the program op- eration. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit can- not be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bit to indicate the oper- ation was successful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the sy stem to primarily program to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle unlock bypass program com- mand sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in description address read data manufacturer id (ba) + 00h 0001h device id, word 1 (ba) + 01h 227eh device id, word 2 (ba) + 0eh 2222h (1.8 v v io , top boot), 2223h (1.8 v v io , bottom boot), 2214h (3.0 v v io , top boot), 2234h (3.0 v v io , bottom boot) device id, word 3 (ba) + 0fh 2200h sector block lock/unlock (sa) + 02h 0001 (locked), 0000 (unlocked) handshaking (ba) + 03h 43h (reduced wait-state), 42h (standard)
32 AM29BDS320G 27243b1 october 1, 2003 preliminary the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. the host system may also initiate the chip erase and sector erase sequences in the unlock bypass mode. the erase command sequences are four cycles in length instead of six cycles. table 14, ?command definitions,? on page 36 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode, only the unlock bypass program, unlock bypass sector erase, unlock bypass chip erase, and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle un- lock bypass reset command sequence. the first cycle must contain the bank address and the data 90h. the second cycle need only contain the data 00h. the bank then returns to the read mode. the device offers accelerated program operations through the acc input. when the system asserts v id on this input, the device au tomatically enters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the acc input to ac- celerate the operation. figure 2 illustrates the algorithm for the program operation. refer to the erase/ program operations table in the ac characteristics section for parameters, and figure 21, ?asynchronous program operation timings,? on page 58 for timing diagrams. figure 2. erase operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress
october 1, 2003 27243b1 AM29BDS320G 33 preliminary the system to preprogram prior to erase. the embedded erase algorithm auto- matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is no t required to provide any controls or tim- ings during these operations. table 14, ?command defi nitions,? on page 36 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latche d. the system can determine the status of the erase operation by using dq7 or dq6/dq2. refer to the ?write operation status? section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the chip erase command sequence while the device is in the unlock bypass mode. the command sequence is two cycles in length instead of six cycles. see ta b l e 1 4 for details on the unlock bypass com- mand sequences. figure 2 illustrates the algorithm for the erase operation. refer to the erase/pro- gram operations table in the ac characteristics section for parameters and timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. ta b l e 1 4 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em- bedded erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electr ical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 35 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise era- sure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor inter- rupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. th e system must rewrite the command se- quence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see ?dq3: sector erase timer? section on page 42 .). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can determine the status of the erase operation by reading
34 AM29BDS320G 27243b1 october 1, 2003 preliminary dq7 or dq6/dq2 in the erasing bank. refer to the ?write operation status? sec- tion on page 37 section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. the host system may also initiate the sector erase command sequence while the device is in the unlock bypass mode. the command sequence is four cycles cycles in length instead of six cycles. figure 2 illustrates the algorithm for the erase operation. refer to the erase/pro- gram operations table in the ac characteristics section for parameters and timing diagrams. erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this com- mand is valid only during the sector erase operation, including the minimum 50 s time-out period during the sector erase command sequence. the erase sus- pend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time- out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the bank enters the erase-sus- pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta- tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits , just as in the standard program op- eration. refer to the ?write operation status? section for more information. in the erase-suspend-read mode, the syst em can also issue the autoselect com- mand sequence. refer to the ?autoselect functions? section on page 16 and ?autoselect command sequence? section on page 30 sections for details. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writ- ing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
october 1, 2003 27243b1 AM29BDS320G 35 preliminary note: see table 14 for program command sequence. figure 3. program operation start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
36 AM29BDS320G 27243b1 october 1, 2003 preliminary command definitions ta b l e 1 4 . command definitions command sequence (notes) cycles bus cycles (notes 1 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read (6) 1 ra rd reset (7) 1 xxx f0 autoselect (8) manufacturer id 4 555 aa 2aa 55 (ba)555 90 (ba)x00 0001 device id (9) 6 555 aa 2aa 55 (ba)555 90 (ba)x01 227e (ba)x 0e (note 9) (ba) x0f 2200 sector lock verify (10) 4 555 aa 2aa 55 (sa)555 90 (sa)x02 0000/0001 handshaking option (11) 4 555 aa 2aa 55 (ba)555 90 (ba)x03 0042/0043 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (12) 2 xxx a0 pa pd unlock bypass sector erase (12) 2 xxx 80 sa 30 unlock bypass chip erase (12) 2 xxx 80 xxx 10 unlock bypass reset (13) 2 ba 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (7, 14) 1 ba b0 erase resume (15) 1 ba 30 sector lock/unlock (7) 3 ba 60 ba 60 sla 60 set burst mode configuration register (16) 3 555 aa 2aa 55 (cr)555 c0 cfi query (17) 1 55 98 legend: x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses latch on the rising edge of the avd# pulse. pd = data to be programmed at location pa. data latches on the rising edge of we# pulse. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a20?a13 uniquely select any sector. ba = address of the bank (a20, a19) that is being switched to autoselect mode, is in bypass mode, is being erased, or is being selected for sector lock/unlock. sla = address of the sector to be locked. set sector address (sa) and either a6 = 1 for unlocked or a6 = 0 for locked. cr = configuration register address bits a19?a12. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a20?a12 are don?t cares. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address. see the autoselect command sequence section for more information. 9. the data in the fifth cycle is 2222 for 1.8 v v io , and 2214 for 3.0 v v io (top boot); 2223 for 1.8 v v io , and 2234 for 3.0 v v io (bottom boot). 10. the data is 0000h for an unlocked sector and 0001h for a locked sector 11. the data is 0043h for reduced wait-state handshaking and 0042h for standard handshaking. 12. the unlock bypass command sequence is required prior to this command sequence. 13. the unlock bypass reset command is required to return to reading array data when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during the erase suspend mode, and requires the bank address. 16. see ?set burst mode configuration register command sequence? for details. 17. command is valid when device is ready to read array data or when device is in autoselect mode.
october 1, 2003 27243b1 AM29BDS320G 37 preliminary write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 16, ?write operation status,? on page 42 and the following subsections describe the function of these bits. dq7 and dq6 each offers a method for determining whether a program or erase op- eration is complete or in progress. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com- plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro- gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1 ? on dq7. the system must provide an address within any of the sectors select ed for erasure to read valid status in- formation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the bank returns to the read mode. if not al l selected sectors are protected, the em- bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if th e system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq6?dq0 while output enable (oe#) is as- serted low. that is, the device may chan ge from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6?dq0 may be still invalid. valid data on dq7?dq0 will appear on successive read cycles. ta b l e 1 6 shows the outputs for data# polling on dq7. figure 3 shows the data# polling algorithm. figure 27, ?data# polling timings (during embedded algorithm),? on page 64 in the ac characteristics section shows the data# polling timing diagram.
38 AM29BDS320G 27243b1 october 1, 2003 preliminary notes: 1. va = valid address for programming. duri ng a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simulta- neously with dq5. figure 4. data# polling algorithm rdy: ready the rdy is a dedicated output that, by defa ult, indicates (when at logic low) the system should wait 1 clock cycle before expecting the next word of data. using the rdy configuration command sequence, rdy can be set so that a logic low indicates the system should wait 2 clock cycles before expecting valid data. rdy functions only while reading data in burst mode. the following conditions cause the rdy output to be low: during the initial access (in burst mode), and after the boundary that occurs every 64 words beginning with the 64th address, 3fh. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start
october 1, 2003 27243b1 AM29BDS320G 39 preliminary dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the same bank, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy- cles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac- tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en- ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter- natively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a pr otected sector, dq6 toggles for approxi- mately 1 ms after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. see the following for additional informatio n: figure 4 (toggle bit flowchart), dq6: toggle bit i (description), figure 28, ?toggle bit timings (during embedded algorithm),? on page 64 (toggle bit timing diagram), and table 15, ?dq6 and dq2 indications,? on page 41 .
40 AM29BDS320G 27243b1 october 1, 2003 preliminary note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information. figure 5. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is ac- tively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0
october 1, 2003 27243b1 AM29BDS320G 41 preliminary sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to ta b l e 1 5 to compare outputs for dq2 and dq6. see the following for a dditional information: figure 5, ?toggle bit algorithm,? on page 40, see ?dq6: toggle bit i? on page 39., figure 28, ?toggle bit timings (during embedded algorithm),? on page 64 , and table 15, ?dq6 and dq2 indi- cations,? on page 41 . ta b l e 1 5 . dq6 and dq2 indications reading toggle bits dq6/dq2 refer to figure 4 for the following discussion. whenever the system initially be- gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has comple ted the program or erase operation. the system can read array data on dq7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system in itially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de- scribed in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of figure 4). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified inter- nal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle. erase suspended, at an address within a sector selected for erasure, does not toggle, toggles. at an address within sectors not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend at any address, toggles, is not applicable.
42 AM29BDS320G 27243b1 october 1, 2003 preliminary the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspen d-read mode if a bank was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de- termine whether or not erasure has beg un. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as- sumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further comman ds (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi- tional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 1 6 shows the status of dq3 relative to the other status bits. ta b l e 1 6 . write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs arra y data if the system addresses a non-busy bank. 4. the system may read either asynchronously or synchron ously (burst) while in erase suspend. rdy will function exactly as in non-erase-suspended mode. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode erase-suspend- read (note 4) erase suspended sector 1 no toggle 0 n/a toggle non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
october 1, 2003 27243b1 AM29BDS320G 43 preliminary absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: all inputs and i/os except as noted below (note 1) . . . . ?0.5 v to v io + 0.5 v v cc (note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +2.5 v v io . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .?0.5 v to +3.5 v acc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +12.5 v output short circuit current (note 3)100 ma notes: 1. minimum dc voltage on input or i/os is ?0 .5 v. during voltage transitions, inputs or i/os may undershoot v ss to ?2.0 v for periods of up to 20 ns during voltage transitions inputs might overshoot to v cc +0.5 v for periods up to 20 ns. see figure 6 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions outputs may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 7 . 2. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 3. stresses above those listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute max- imum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . .+1.65 v to +1.95 v v io supply voltages: v io v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1.65 v to +1.95 v v io > v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 to +3.15 v operating ranges define those limits between which the functionality of the device is guaranteed. figure 6. maximum negative overshoot waveform figure 7. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
44 AM29BDS320G 27243b1 october 1, 2003 preliminary dc characteristics cmos compatible notes: 1. maximum i cc specifications are tested with v cc = v cc max. 2. all i cc specifications are tested with v io = v cc. 3. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 4. i cc active while embedded erase or embedded program is in progress. 5. device enters automatic sleep mode when addresses are stable for t acc + 60 ns. typical sleep mode current is equal to i cc3 . parameter description test conditions (note 1,2) min typ. max unit i li input load current v in = v ss to v cc , v cc = v cc max 1 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1 a i ccb v cc active burst read current ce# = v il , oe# = v ih , we# = v ih, 54 mhz 10 20 ma ce# = v il , oe# = v ih , we# = v ih, 40 mhz 816ma i io v io non-active output v io = 1.8 v, oe# = v ih 0.2 10 a v io = 3.0 v, oe# = v ih 0.2 10 a i cc1 v cc active asynchronous read current (note 3) ce# = v il , oe# = v ih , we# = v ih 5 mhz 12 16 ma 1 mhz 3.55ma i cc2 v cc active write current (note 4) ce# = v il , oe# = v ih , v pp = v ih 15 40 ma i cc3 v cc standby current (note 5) ce# = reset# = v cc 0.2 v 0.2 10 a i cc4 v cc reset current reset# = v il, clk = v il 0.2 10 a i cc5 v cc active current (read while write) ce# = v il , oe# = v ih 25 60 ma v il input low voltage v io = 1.8 v ?0.5 0.2 v v io = 3.0 v ?0.5 0.4 v v ih input high voltage v io = 1.8 v v io ? 0.2 v io + 0.2 v v io = 3.0 v v io ? 0.4 v io + 0.4 v v ol output low voltage i ol = 100 a, v cc = v cc min , v io = v io min 0.1 v v oh output high voltage i oh = ?100 a, v cc = v cc min , v io = v io min v io ? 0.1 v v id voltage for accelerated program 11.5 12.5 v v lko low v cc lock-out voltage 1.0 1.4 v
october 1, 2003 27243b1 AM29BDS320G 45 preliminary test conditions key to switching waveforms switching waveforms figure 9. input waveforms and measurement levels note: diodes are in3064 or equivalent figure 8. test setup table 17. test specifications c l device under test test condition all speed options unit output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v output measurement level input v io /2 v io /2 all inputs and outputs
46 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics v cc and v io power-up figure 10. v cc and v io power-up diagram parameter description test setup speed unit t vcs v cc setup time min 50 s t vios v io setup time min 50 s t rsth reset# low hold time min 50 s v cc v io reset# t vcs t rsth t vios
october 1, 2003 27243b1 AM29BDS320G 47 preliminary ac characteristics synchronous/burst read note: addresses are latched on the first of either the active edge of clk or the rising edge of avd#. parameter description d8 (54 mhz) d3 (54 mhz) c8 (40 mhz) c3 (40 mhz) unit jedec standard t iacc latency (even address in reduced wait-state handshaking mode) max 87.5 95 ns parameter description d8, d9 (54 mhz) d3, d4 (54 mhz) c8, c9 (40 mhz) c3, c4 (40 mhz) unit jedec standard t iacc latency?(standard handshaking or odd address in handshake mode) max 106 120 ns t bacc burst access time valid clock to output delay max 13.5 20 ns t acs address setup time to clk (note note:) min 5 ns t ach address hold time from clk (note note:) min 7 ns t bdh data hold time from next clock cycle min 3 ns t oe output enable to output valid max 13.5 20 ns t cez chip enable to high z max 10 10.5 10 10.5 ns t oez output enable to high z max 10 10.5 10 10.5 ns t ces ce# setup time to clk min 5 ns t rdys rdy setup time to clk min 5 4.5 5 4.5 ns t racc ready access time from clk max 13.5 14 20 20 ns t aas address setup time to avd# (note note:) min 5 ns t aah address hold time to avd# (note note:) min 7 ns t cas ce# setup time to avd# min 0 ns t avc avd# low to clk min 5 ns t avd avd# pulse min 12 ns t acc access time max 70 ns
48 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. 2. if any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by rdy. 3. the device is in synchronous mode. figure 11. clk synchronous burst mode read (rising active clk) da da + 1 da + n oe# dq15 - dq0 a20 - a0 aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t racc t oez t cez t iacc t acc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 12 3456 7 t rdys t bacc
october 1, 2003 27243b1 AM29BDS320G 49 preliminary ac characteristics notes: 1. figure shows total number of wait states set to four cycl es. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active falling edge. 2. if any burst address occurs at a 64-word boundary, one a dditional clock cycle is insert ed, and is indicated by rdy. 3. the device is in synchronous mode. 4. in the burst mode configuration register, a17 = 0. figure 12. clk synchronous burst mode read (falling active clock) da da + 1 da + n oe# dq15-dq0 a20-a0 aa avd# rdy clk ce# t ces t acs t avc t avd t ach t oe t oez t cez t iacc t acc t bdh 4 cycles for initial access shown. t racc hi-z hi-z hi-z 12345 t rdys t bacc
50 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, one a dditional clock cycle is insert ed, and is indicated by rdy. 3. the device is in synchronous mode. 4. in the burst mode configuration register, a17 = 1. figure 13. synchronous burst mode read note: figure assumes 7 wait states for initial access, 54 mhz clock, and automatic detect synchronous read. d0?d7 in data waveform indicate the order of data within a given 8-word address range, from lowest to highest. data will wrap around within the 8 words non-stop unless the reset# is a sserted low, or avd# latches in another address. starting address in figure is the 7th address in range (a6). see ?requirements for synchronous (burst) read operation?. the set configuration register command sequence has been writte n with a18=1; device will output rdy with valid data. figure 14. 8-word linear burst with wrap around da da + 1 da + n oe# dq15-dq0 a20-a0 aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc d6 d7 oe# dq15-dq0 a20-a0 aa avd# rdy clk ce# t ces t acs t avds t avd t ach t oe t iacc t bdh d0 d1 d5 d6 7 cycles for initial access shown. 18.5 ns typ. (54 mhz) hi-z t racc 1 234567 t rdys t bacc t acc
october 1, 2003 27243b1 AM29BDS320G 51 preliminary ac characteristics note: figure assumes 6 wait states for initial access, 40 mhz clock, and synchronous read. the set configuration reg- ister command sequence has been written with a18=0; device will output rdy one cycle before valid data. figure 15. burst with rdy set one cycle before data d1 d0 d2 d3 da + n oe# dq15-dq0 a20-a0 aa avd# rdy clk ce# t ces t acs t avds t avd t ach t oe t racc t oez t cez t iacc t bdh 6 wait cycles for initial access shown. 25 ns typ. (40 mhz) hi-z hi-z hi-z 1 23456 t rdys t bacc t acc
52 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, one a dditional clock cycle is insert ed, and is indicated by rdy. 3. the device is in synchronous mode. 4. this waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a clk synchronous burst mode. figure 16. reduced wait-state handshaking burst mode read starting at an even address da da + 1 da + n oe# dq15-dq0 a20-a0 aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 1234567 t rdys t bacc t acc
october 1, 2003 27243b1 AM29BDS320G 53 preliminary ac characteristics figure 17. reduced wait-state handshaking burst mode read starting at an odd address notes: 1. figure shows total number of wait states set to seven cycles. the total number of wait states can be programmed from two cycles to seven cycles. clock is set for active rising edge. 2. if any burst address occurs at a 64-word boundary, one a dditional clock cycle is insert ed, and is indicated by rdy. 3. the device is in synchronous mode. 4. this waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under a clk synchronous burst mode. da da + 1 da + n oe# dq15-dq0 a20-a0 aa avd# rdy clk ce# t cas t aas t avc t avd t aah t oe t racc t oez t cez t iacc t bdh 7 cycles for initial access shown. hi-z hi-z hi-z 12345 78 t rdys t bacc t acc 6
54 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics asynchronous read notes: 1. asynchronous access time is from the last of either stable addresses or the falling edge of avd#. 2. not 100% tested. note: ra = read address, rd = read data. figure 18. asynchronous mode read with latched addresses parameter description d3, d4 d8, d9 (54 mhz) c3, c4 c8, c9 (40 mhz) unit jedec standard t ce access time from ce# low max 70 90 ns t acc asynchronous access time (note 1) max 70 90 ns t avdp avd# low time min 12 ns t aavds address setup time to rising edge of avd min 5 ns t aavdh address hold time from rising edge of avd min 7 ns t oe output enable to output valid max 13.5 20 ns t oeh output enable hold time read min 0 ns toggle and data# polling min 10 ns t oez output enable to high z (note 2) max 10 10.5 ns t cas ce# setup time to avd# min 0 ns t ce we# a20-a0 ce# oe# valid rd t acc t oeh t oe dq15-dq0 t oez t aavdh t avdp t aavds avd# ra t cas
october 1, 2003 27243b1 AM29BDS320G 55 preliminary ac characteristics note: ra = read address, rd = read data. figure 19. asynchronous mode read t ce we# a20-a0 ce# oe# valid rd t acc t oeh t oe dq15-dq0 t oez avd# ra
56 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics hardware reset (reset#) note: not 100% tested. figure 20. reset timings parameter description all speed options unit jedec std t readyw reset# pin low (during embedded algorithms) to read mode (see note) max 35 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 200 ns t rpd reset# low to standby mode min 20 s reset# t rp t readyw reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp
october 1, 2003 27243b1 AM29BDS320G 57 preliminary ac characteristics erase/program operations notes: 1. not 100% tested. 2. in asynchronous timing, addresses are latched on the falling edge of we#. in synchronous mode, addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 3. see the ?erase and programming performance? section for more information. 4. does not include the preprogramming time. parameter description all speed options unit jedec standard t avav t wc write cycle time (note 1) min 80 ns t avwl t as address setup time (note 2) synchronous min 5 ns asynchronous 0 t wlax t ah address hold time (note 2) synchronous min 7 ns asynchronous 45 t acs address setup time to clk (note 2) min 5 ns t ach address hold time to clk (note 2) min 7 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t ghwl t ghwl read recovery time before write min 0 ns t cas ce# setup time to avd# min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 50 ns t whwl t wph write pulse width high min 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 3) typ 8 s t whwh1 t whwh1 accelerated programming operation (note 3) typ 2.5 s t whwh2 t whwh2 sector erase operation (notes 3, 4) typ 0.4 sec chip erase operation (notes 3, 4) 28 t vid v acc rise and fall time min 500 ns t vids v acc setup time (during accelerated programming) min 1 s t vcs v cc setup time min 50 s t csw1 clock setup time to we# (asynchronous) min 5 ns t csw2 clock setup time to we# (synchronous) min 1 ns t chw clock hold time from we# max 1 ns t elwl t cs ce# setup time to we# min 0 ns t avsw avd# setup time to we# min 5 ns t avhw avd# hold time to we# min 5 ns t avhc avd# hold time to clk min 5 ns t avdp avd# low time min 12 ns
58 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a20?a12 are don?t care during command sequence unlock cycles. 4. the asynchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. figure 21. asynchronous program operation timings oe# ce# data addresses avd we# clk v cc 555h pd t as t avsw t avhw t csw1 t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs
october 1, 2003 27243b1 AM29BDS320G 59 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a20?a12 are don?t care during command sequence unlock cycles. 4. the asynchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. figure 22. alternate asynchronous program operation timings oe# ce# data addresses avd we# clk v cc 555h pd t as t avsw t avhw t chw t ah t wc t wph pa t vcs t wp t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds v ih v il t avdp a0h t cs
60 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a20?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either cs# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. 7. clk must not have an active edge while we# is at v il . 8. avd# must toggle during command sequence unlock cycles. figure 23. synchronous program operation timings oe# ce# data addresses avd we# clk v cc 555h pd t as t wp t ah t wc t wph pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t avsw t acs t cas t csw2
october 1, 2003 27243b1 AM29BDS320G 61 preliminary ac characteristics notes: 1. pa = program address, pd = program data, va = valid address for reading status bits. 2. ?in progress? and ?complete? refer to status of program operation. 3. a20?a12 are don?t care during command sequence unlock cycles. 4. addresses are latched on the first of either the rising edge of avd# or the active edge of clk. 5. either cs# or avd# is required to go from low to high in between programming command sequences. 6. the synchronous programming operation is independent of the set device read mode bit in the burst mode configuration register. 7. avd# must toggle during command sequence unlock cycles. 8. t ah = 45 ns. 9. clk must not have an active edge while we# is at v il . figure 24. alternate synchronous program operation timings oe# ce# data addresses avd we# clk v cc 555h pd t ah t wc t wph t wp pa t vcs t dh t ch in progress t whwh1 va complete va program command sequence (last two cycles) read status data t ds t avdp a0h t acs t cas t avhc t csw2 t as (note 8)
62 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics figure 25. chip/sector erase command sequence notes: 1. sa is the sector address for sector erase. 2. address bits a20 ?a12 are don?t cares during unlock cycles in the command sequence. oe# ce# data addresses avd# we# clk v cc t as t wp t ah t wc t wph sa t vcs t cs t dh t ch in progress t whwh2 va complete va erase command sequence (last two cycles) read status data t ds 10h for chip erase 555h for chip erase v ih v il t avdp 55h 2aah 30h
october 1, 2003 27243b1 AM29BDS320G 63 preliminary ac characteristics note: use setup and hold times from conventional program operation. figure 26. accelerated unlock bypass programming timing ce# avd# we# addresses data oe# acc don't care don't care a0h don't care pa pd v id 1 ms v il or v ih t vid t vids
64 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, and data# polling will output true data. 3. avd# must toggle between data reads. figure 27. data# polling timings (during embedded algorithm) notes: 1. status reads in figure are shown as asynchronous. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. avd# must toggle between data reads. figure 28. toggle bit timings (during embedded algorithm) we# ce# oe# t oe addresses avd# t oeh t ce t ch t oez t cez status data status data t acc va va data we# ce# oe# t oe addresses data avd# t oeh t ce t ch t oez t cez status data status data t acc va va
october 1, 2003 27243b1 AM29BDS320G 65 preliminary ac characteristics notes: 1. the timings are similar to synchronous read timings. 2. va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (a18 = 0 in the burst mode configuration register). when a18 = 1 in the burst mode configuration register, rdy is acti ve one clock cycle before data. 4. avd# must toggle between data reads. figure 29. synchronous data polling timings/toggle bit timings ce# clk avd# addresses oe# data rdy status data status data va va t iacc t iacc
66 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics notes: 1. rdy active with data (a18 = 1 in the burst mode configuration register). 2. rdy active one clock cycle before data (a18 = 0 in the burst mode configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device not crossing a bank in the process of performing an erase or program. figure 30. latency with boundary crossing clk address (hex) c60 c61 c62 c63 c63 c63 c64 c65 c66 c67 d60 d61 d62 d63 d64 d65 d66 d67 (stays high) avd# rdy data oe#, ce# (stays low) address boundary occurs every 64 words, beginning at address 00003fh (00007fh, 0000bfh, etc.). address 000000h is also a boundary crossing. 3c 3d 3e 3f 3f 3f 40 41 42 43 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc
october 1, 2003 27243b1 AM29BDS320G 67 preliminary ac characteristics notes: 1. rdy active with data (a18 = 1 in the burst mode configuration register). 2. rdy active one clock cycle before data (a18 = 0 in the burst mode configuration register). 3. cxx indicates the clock that triggers dxx on the outputs; for example, c60 triggers d60. figure shows the device crossing a bank in the process of performing an erase or program. figure 31. latency with boundary crossing into program/erase bank clk address (hex) c60 c61 c62 c63 c63 c63 c64 d60 d61 d62 d63 read status (stays high) avd# rdy data oe#, ce# (stays low) address boundary occurs every 64 words, beginning at address 00003fh (00007fh, 0000bfh, etc.). address 000000h is also a boundary crossing 3c 3d 3e 3f 3f 3f 40 latency rdy latency t racc (note 1) (note 2) t racc t racc t racc invalid
68 AM29BDS320G 27243b1 october 1, 2003 preliminary ac characteristics note: a14, a13, a12 = ?101? ? 5 programmed, 7 total a14, a13, a12 = ?100? ? 4 programmed, 6 total a14, a13, a12 = ?011? ? 3 programmed, 5 total a14, a13, a12 = ?010? ? 2 programmed, 4 total a14, a13, a12 = ?001? ? 1 programmed, 3 total a14, a13, a12 = ?000? ? 0 programmed, 2 total figure assumes address d0 is not at an address boundary, active clock edge is rising, and wait state is set to ?101?. figure 32. example of wait states insertion (standard handshaking device) data avd# oe# clk 12345 d0 d1 01 6 2 7 3 total number of clock cycles following avd# falling edge rising edge of next clock cycle following last wait state triggers next burst data number of clock cycles programmed 45
october 1, 2003 27243b1 AM29BDS320G 69 preliminary ac characteristics note: breakpoints in waveforms indicate that system may alte rnately read array data from the ?non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. the system should read status twice to ensure valid information. figure 33. back-to-back read/write cycle timings oe# ce# we# t oeh data addresses avd# pd/30h aah ra pa/sa t wc t ds t dh t rc t rc t oe t as t ah t acc t oeh t wp t ghwl t oez t wc t sr/w last cycle in program or sector erase command sequence read status (at least two cycles) in same bank and/or array data from other bank begin another write or program command sequence rd ra 555h rd t wph
70 AM29BDS320G 27243b1 october 1, 2003 preliminary erase and programming performance notes: 1. typical program and erase times as sume the following conditions: 25 c, 1.8 v v cc , 1 million cycles. additionally, programming typicals assumes a checkerboard pattern. 2. under worst case conditions of 90c, v cc = 1.65 v, 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all words are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 14 for further information on command definitions. 6. the device has a minimum erase and prog ram cycle endurance of 1 million cycles. fbga ball capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.4 5 s excludes 00h programming prior to erasure (note 4) chip erase time 28 s word programming time 11.5 210 s excludes system level overhead (note 5) accelerated word programming time 4 120 s chip programming time (note 3) 25 75 s excludes system level overhead (note 5) accelerated chip programming time 9 27 s parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4.2 5.0 pf c out output capacitance v out = 0 5.4 6.5 pf c in2 control pin capacitance v in = 0 3.9 4.7 pf parameter test conditions min unit minimum pattern data retention time 150 c10 years 125 c20 years
october 1, 2003 27243b1 AM29BDS320G 71 preliminary physical dimensions vbd064?64-ball fine-pitch ball grid array (fbga) 8 x 9 mm package note: bsc is an ansi standard for basic space centering. package vbd 064 jedec n/a 8.95 mm x 7.95 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.20 --- 0.30 ball height a2 0.62 --- 0.76 body thickness d 8.95 bsc. body size e 7.95 bsc. body size d1 5.60 bsc. ball footprint e1 5.60 bsc. ball footprint md 8 row matrix size d direction me 8 row matrix size e direction n 64 total ball count b 0.30 0.35 0.40 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement none depopulated solder balls notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. side view a2 a seating plane c c c 0.10 0.08 a1 top view 10 c (2x) 0.05 (2x) c 0.05 a b index mark corner pin a1 e d bottom view a1 corner sd se 7 e1 e d1 ab nx b m 0.15 0.08 m c c 6 g h 8 6 5 4 3 2 1 b a 7 d c e f
72 AM29BDS320G 27243b1 october 1, 2003 preliminary revision summary revision a (november 22, 2002) initial release. revision a + 1 (march 7, 2003) autoselect command sequence updated table 3. command definitions updated table 14, device id sixth cycle. revision b (august 12, 2003) global updated formatting to new spansion template. sector lock/unlock command sequence modified description of write cycles. reset command modified last paragraph of section. table 14 , command definitions added note references to erase suspend and sector lock/unlock rows in table. replaced addresses ?xxx? with ?ba? in first and second cycles of sector lock/un- lock table row. modified description of ba in legend. revision b + 1 (october 1, 2003) dc characteristics - cmos compatible added note #2. modified column heading fr om test conditions (note 1) to test conditions (note 1,2). trademarks and notice this document contains fasl confidential information. the contents of this document may not be copied nor duplicated in any for m, in whole or in part, without prior written consent from fasl. the information in this document is subject to change without notice. product and comp any names are trademarks or registered trademarks of their respective owners copyright 2003 fasl llc. all rights reserved.

▲Up To Search▲

Price & Availability of AM29BDS320G

	To Download AM29BDS320G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .